FIG. 6 is a perspective view illustrating a two-dimensional imaging array. This array includes a two-dimensional array of photodiodes 1, for example, 128.times.128 photodiodes, for generating electrical signals in response to light incident on the respective photodiodes. The photodiode array is mounted on and electrically connected to a p type silicon substrate 50a containing signal processing circuitry. Each photodiode is in electrical communication with a respective signal processing circuit in the substrate 50a through a columnar body 30, such as a cylindrical volume of indium. This construction is particularly applicable to an infrared light detector in which incident infrared light 200 strikes the photodiode array 1. The photodiode array 1 comprises cadmium mercury telluride (Cd.sub.0.2 Hg.sub.0.8 Te) that responds to infrared light in 10 micron band.
The general electrical arrangement of the imaging array of FIG. 6 is shown schematically in FIG. 7. For simplicity, FIG. 7 shows a 3.times.3 array of photodiodes 1a to 1i, i.e., an array including three photodiodes in each of three rows. The photodiodes 1a to 1i are connected to the source regions of vertical switch MOS transistors 2a to 2i, respectively, via the columnar connectors 30. A vertical scanner 3 is commonly connected to the gate electrodes of the vertical switch MOS transistors 2a to 2i. The drain regions of the vertical switch MOS transistors 2a to 2i are connected to charge storage capacitors 4x, 4y, and 4z. The charge storage capacitors 4x, 4y, and 4z are connected to the source regions of horizontal switch MOS transistors 5a, 5b, and 5c, respectively. A vertical scanner 6 is commonly connected to the gate electrodes of the horizontal switch MOS transistors 5a to 5c. A floating diffusion amplifier (hereinafter referred to as FDA) output circuit 7 is commonly connected to the drain regions of the horizontal switch MOS transistors 5a to 5c. Reference numeral 8 designates an output terminal.
In operation, incident light causes the photodiodes 1a to 1i to produce electrical charges that are conducted through the indium connectors 30 to the respective vertical switch MOS transistors 2a to 2i. Receiving clock pulses from the vertical scanner 3, the vertical switch MOS transistors in each column transfer electrical charges to one of the charge storage capacitors 4x to 4z. Receiving clock pulses from the horizontal scanner 6, the horizontal switch MOS transistor transfers electrical charges stored in the charge storage capacitor to the FDA output circuit 7.
FIGS. 9(a) to 9(c) are schematic diagrams illustrating the signal processing circuitry of the infrared imaging device and potential wells produced in the p type silicon substrate 50a. In the figures, the same reference numerals as in FIG. 7 designate the same or corresponding parts. Reference numeral 1A designates a photodiode arbitrarily selected from the photodiodes 1a to 1i. Reference numeral 2 designates one of the vertical switch MOS transistors 2a to 2i which corresponds to the photodiode 1A. Reference numeral 4 designates one of the charge storage capacitors 4x to 4z, which corresponds to the photodiode 1A. The charge storage capacitor 4 includes an injection gate 4a and a storage gate 4b. Reference numeral 5 designates one of the horizontal switch MOS transistors 5a to 5c, which corresponds to the charge storage capacitor 4. Reference numerals 11 and 12 designate an input diode and an output diode, respectively. The FDA output circuit 7 includes an FDA output gate 7a, an FDA source follower 7b connected to the FDA output gate 7a, and a resistance 7c connected between the FDA output gate 7b and the ground. Reference numeral 9 designates an FDA overflow reset gate for draining electrical charges stored in the potential well created opposite the output diode 12 to an FDA reset drain 10. Reference numeral 13 designates an FDA overflow reset gate for draining electrical charges stored in the potential well created opposite the storage gate 4b to an overflow drain 14. All of the gates described above are by MOS switches. In FIGS. 9(a)-9(c), for convenience, the vertical switch MOS transistor 2, the FDA overflow reset gate 9, the FDA reset drain 10, the FDA output circuit 7, the FDA overflow reset gate 13, and the overflow drain 14 are shown disposed apart from the p type silicon substrate 50a. However, these elements are included in the substrate 50a.
FIG. 8 is a block diagram illustrating an infrared imaging apparatus in which the imaging array 50 is interconnected with other components. Electrical charges output from the infrared imaging array 50 are converted to electrical imaging signals by a scan converter 51 and displayed on a television monitor 52 as a visible image. To coordinate the reading out of the sequential electrical imaging signals from the array 50 with the conversion of those signals into a two-dimensional image in the scan converter 51, a timing generator 53 provides timing signals to both the array 50 and the scan converter 51.
FIG. 10 is a schematic diagram showing clock pulses .phi.V, .phi.RS, .phi.R, and H1 applied to the respective gate terminals of the infrared imaging array 50 and the voltage waveform of an output signal DVo 1 from the output terminal 8. The clock pulses .phi.V and .phi.H1 are generated from the vertical scanner 3 and the horizontal scanner 6, respectively, and the clock pulses .phi.RS and .phi.R are generated from other scanners (not shown). The timing of each clock pulse is determined by the timing generator 53 of FIG. 8.
A description is given of the operation of the infrared imaging array.
When the clock pulse .phi.V from the vertical scanner 3 is applied to the gate of the vertical switch MOS transistor (hereinafter referred to as a vertical scanner gate) 2, three photodiodes in a prescribed row, for example, the photodiodes 1a, 1b, and 1c in the uppermost row shown in FIG. 6, are selected from the photodiodes 1a to 1i.
Turning to FIG. 9(a), when the clock pulse .phi.RS applied to the overflow electrode 13 and the clock pulse .phi.V applied to the vertical scanner gate 2 are both at "H" level, electrical charges generated in the photodiode 1A, which is one of the three photodiodes selected, are transferred through the vertical scanner gate 2 and a potential well created opposite the input diode 11 to a potential well created opposite the storage gate 4b, and then the electrical charges are drained through the overflow electrode 13 to the overflow drain 14. When the clock pulse .phi.RS decreases to "L" level to close the overflow electrode 13, electrical charges transferred from the photodiode 1A are accumulated in the potential well beneath the storage gate 4b. After the charge accumulation, when the clock pulse .phi.R applied to the FDA reset gate 9 increases to "H" level to open the FDA reset gate 9, the potential of the output diode 12 increases and a high voltage is applied to the output terminal 8 because a constant voltage power supply (not shown) is connected to the FDA reset drain 10. Then, the clock pulse .phi.R decreases to "L" level to produce a potential well beneath the output diode 12. In this state, when the read-out clock pulse .phi.H1 recurring at regular intervals shown in FIG. 10 is applied to the gate of the horizontal switch MOS transistor (hereinafter referred to as horizontal scanner gate) 5, the electrical charges stored in the potential well beneath the storage gate 4b are transferred to the potential well beneath the output diode 12 while the clock pulse .phi.H1 is at "H" level, i.e., while the horizontal scanner gate 5 is open (FIG. 9(c)). The width of each pulse of the read-out clock .phi.H1 corresponds to the time interval required for opening one horizontal scanner gate 5. Receiving the read-out clock pulse .phi.H1, the horizontal scanner gates 5a, 5b, and 5c successively open in this order and electrical charges stored in the charge storage capacitors 4x, 4y, and 4z are successively read out. The gate voltage of the FDA output gate 7a changes during every transfer of electrical charges stored in the charge storage capacitor 4 to the output diode 12, and the current flowing to the FDA output gate 7a from the constant-voltage source connected to the FDA source follower 7b is reduced, whereby the output signal DVo 1 having a voltage shape shown in FIG. 10 is output from the output terminal 8.
In the above-described operation, the pulse width of the read-out clock .phi.H1 is equivalent to the time interval for reading out electrical charges of one photodiode, i.e., pixel, and this charge read-out time interval is usually as long as or a little longer than the time interval during which electrical charges stored in the potential well beneath the storage gate 4b are completely transferred to the potential well beneath the output diode 12. Hereinafter, this time interval is called an actual read-out time.
In the above-described operation, before transferring electrical charges to the potential well beneath the output diode 12, a "H" level pulse is applied to the FDA reset gate 9 to completely eliminate electrical charges from the potential well beneath the output diode 12 during every reading out of electrical charges for each pixel.
FIG. 11(a) is a plan view illustrating the charge storage gate 4b and its vicinity and FIG. 11(b) is a sectional view taken along line XIb--XIb of FIG. 11(a). In the figures, the same reference numerals as in FIGS. 6, 7, and 9(a)-9(c) designate the same or corresponding parts. Reference numeral 60 designates an insulating film about 500 angstroms thick comprising silicon oxide. As shown in FIG. 11(a), the storage gate 4b of the charge storage capacitor 4 is long and narrow in the charge transfer direction to increase the volume of the potential well created opposite the storage gate 4b, whereby a large quantity of electrical charges generated in the photodiode are stored in the potential well. For example, the storage gate 4b has a width of about 80 microns and a length of about 300 microns.
The charge transfer from the potential well beneath the storage gate 4b to the potential well beneath the output diode 12 is carried out by self induced drift of the electrical charge itself and thermal diffusion of the electrical charge due to the heat from the p type substrate. In the initial stage of the charge transfer operation where a lot of electrical charges remain in the potential well beneath the storage gate, the charges are rapidly transferred to the potential well beneath the output diode 12 by the self-induced drift of the charges. However, in the final stage of the charge transfer operation where a small quantity of charges remains in the potential well beneath the storage gate, the self-induced drift of the charge decreases and the charge transfer is carried out only by thermal diffusion, increasing the charge transfer time. That is, the longer the potential well created beneath the storage gate 4b is, the longer the charge transfer time becomes. Therefore, when the length of the storage gate 4b is increased in the charge transfer direction to store a large quantity of electrical charges, in order to completely transfer the electrical charges to the potential well beneath the output diode, the pulse width of the read-out clock .phi.H applied to the vertical scanner gate 5 has to be increased to increase the time interval during which the vertical scanner gate 5 is open, i.e., the time interval for reading out the charges.
Meanwhile, when an output image is displayed on a TV monitor, it takes 1/60 sec. to process one frame. Therefore, when an output signal from the above-described infrared imaging array is displayed on a TV monitor as an image, the pulse width of the read-out clock .phi.H1, i.e., the charge read-out time, is about 1 .mu.s. Recently, an increase in the frame rate, i.e., a reduction in the time required for processing one frame, has been proposed to faithfully capture an image of a target moving at high speed. In this case, however, it is necessary to further reduce the charge read-out time from 1 .mu.s.
In the conventional infrared imaging array described above, however, if the length of the storage gate 4b is increased in the charge transfer direction to increase the quantity of charges stored in the potential well beneath the storage gate 4b, the time required for transferring the charges to the potential well beneath the output diode 12, i.e., the actual read-out time, is increased. In this state, if the pulse width of the read-out clock .phi.H1 applied to the horizontal scanner gate 5, i.e., the actual read-out time, is made lower shorter than 1 .mu.s to operate the imaging array in a TV frame, the quantity of charges transferred from the potential well beneath the storage gate to the potential well beneath the output diode 12 unfavorably decreases, resulting in poor resolution of the image attained.